FPGA - Zedboard - my second FPGA design

Before launching into something new, I want to try something. I find a constraint file for my first project and edit it. Now I start Vivado and go to "Run Synthesis". Indeed it goes ahead and reruns it (warning me I will overwrite prior work) rather than telling me everything is up to date.

Blink an LED

I already have vivado 2021.2 open, so I go to File, Project, New and am greeted by the new project wizard. I call the new project "zed_2".

I add a design source "blink.v". I create 2 output ports, led0 and led1.

Now I go to:

cd /home/tom/zed_2/zed_2.srcs/sources_1/new
vi blink.v

Now, the constraint file. I am going to take the approach of adding a file that I will edit ahead of time (namely the master constraint file with 3 lines uncommented).

cd /u1/Projects/FPGA/Zedboard
cp Zedboard-Master.xdc /home/tom/blink.xdc
cd
vi blink.xdc

Y9 for GCLK (I rename clock)
T22 for led0
T21 for led1

/home/tom/zed_2/zed_2.srcs/constrs_1/imports/tom/blink.xdc

Now I do "Run synthesis" and get an error. I have a semicolon after "input clock" rather than a comma. I fix this with the vivado editor. Now the error is about a license for device xc7vx485t, what the heck? Indeed I look at settings and see this set for the project device (I thought I selected Zedboard??). I change and apply this in settings and try "Run Synthesis" again. This works.

I see a warning about my constraints file. This is for line 370 which sets the voltage for bank 34. Perhaps I should have commented out this line since I have nothing in bank 34. But it is just a warning.

And it works!!

I have two LED blinking away; and it does look like 1 Hz.
Here is the verilog I used:

module blink(
    input clock,
    output led0,
    output led1
    );

parameter p_CNT_1HZ = 50_000_000;

reg [31:0] r_CNT = 0;

reg  r_TOGGLE = 1'b0;

always @ (posedge clock)
    begin
      if (r_CNT == p_CNT_1HZ-1) // -1, since counter starts at 0
        begin
          r_TOGGLE <= !r_TOGGLE;
          r_CNT    <= 0;
        end
      else
        r_CNT <= r_CNT + 1;
    end

    assign led0 = r_TOGGLE;
    assign led1 = r_TOGGLE;

endmodule

I am using ideas from this example:

• Nandland - your first vhdl program

A change

It sure is slow. Vivado has a "status" line at the upper right that you can check if you wonder if it is doing what it is supposed to be doing. But when the smoke clears, this works perfectly, here is the verilog:

module blink(
    input clock,
    input enable,
    output led0,
    output led1
    );

parameter p_CNT_1HZ = 50_000_000;

reg [31:0] r_CNT = 0;

reg  r_TOGGLE = 1'b0;

always @ (posedge clock)
    begin
      if (r_CNT == p_CNT_1HZ-1) // -1, since counter starts at 0
        begin
          r_TOGGLE <= !r_TOGGLE;
          r_CNT    <= 0;
        end
      else
        r_CNT <= r_CNT + 1;
    end

    assign led0 = enable & r_TOGGLE;
    assign led1 = enable & r_TOGGLE;

endmodule