FPGA - Zedboard and Xilinx Vivado tutorials

Now I click on the Vivado desktop icon. This is on my Fedora 35 system and starts Vivado ML edition 2021.2

I use "create project". I call the project zed_1 and tell it to place it in /home/tom. I call it an RTL project. The next page lets me select the part or board. I click on "boards" at the top, then scroll down to "Zedboard". I click Finish, and I have a project started.

Now I am more or less trying to follow the "simplest FPGA in the world" project. I select "Add sources". I add the file "top.v". Now I get a define module dialog. I define ports -

switch -- input, bus, 0,0
led    -- output, bus, 0,0

My file shows [0:0], but the example doesn't -- he must not have clicked "bus" (whatever that is). I edit this out and add the single "assign" line to get:

module top(
    input switch,
    output led
    );
    assign led = switch;
endmodule

Constraints

Switch 0 is pin F22 (a 2.5 volt input)
LED 0 is pin T22 (a 3.3 volt output)

Now in "Sources", there it is under Constraints, constrs_1 (whatever that is). I double click top.xdc and it opens in the box to the right, entirely empty with no boilerplate like top.v had. I copy and paste the following from the tutorial:

set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property IOSTANDARD LVCMOS25 [get_ports switch]
set_property PACKAGE_PIN T22 [get_ports led]
set_property PACKAGE_PIN F22 [get_ports switch]

Another approach to constraints files if to find the master constraint file and then uncomment and edit appropriate lines in it.

• Github: Digilent zedboard master xdc file
• Digilent master xdc constraint files

• Zynq pins - deep dive

The Master constraint file groups things and indicates which bank they are in. Buttons are in bank 34, Switches are in bank 35, so both are 1.8 volt and I should change my constraints file. LED are in bank 33, which is 3.3 volt.

Compile the design

Now I am back up with the Project Manager.
I click "Run Synthesis", it tells me it is up to date, so I cancel.
I click "Run Implementation", it gives me a similar warning, but I re-run anyway.
After the usual long wait with lots of disk noise, I get a dialog announcing completion.
It shows me a cute color X-ray picture of the chip.

I know now that things were hidden at the bottom left "Flow Navigator".
I click "generate bitstream and wait for the completion dialog.
I click "Open hardware manager".
This does not bring up a new GUI, but instead replaces most of the right side of the main Vivado GUI. I guess Project Manager is now replaced with Hardware Manager.
A green bar at the top tells me "no hardware detected" and had blue text "Open target". I click the text and select autoconnect. Lots of stuff happens and a hardware hierarchy appears with two entries: arm_dap_0 and xc7c020_1.
Now there is blue text in the green bar saying "Program device", I click that.
It finds "top.bit" to use as a bitstream. I click the program button.
There is a progress bar, and a bright blue LED comes on on the Zedboard, next to the LCD screen.

And it works!!

I move switch sw0 and LED ld0 comes on accordingly!