November 27, 2024

Antminer S9 board - Vivado -- refresher

I am running Vivado 2022.2 -- I keep getting offered new versions by the "Xilinx Information Center" that is still running on my machine, but I have yet to find any problems with 2022.1 and so why go through extra work.

I type "vivado" at the command line. This is a tiny shell script I wrote that does a cd to my vivado directory and runs the vivado executable from deep in the vivado install bin directory. I do have a desktop shortcut, but generally do not use it.

Under "quick start" I select "create project" and work through their new project wizard. I go with the defaults except as noted. I set the project name. I use "baloney" for this test flight. This is an RTL project and I do not specify sources at this time. The next window lets me select a part, but beware here and change to the "board" tab. Rather than scrolling all the boards at the main part of the window, use the "name" pulldown and fine EBAZ4205 in that selection. Be sure you actually select the EBAZ in the big window below. Then "finish" and you are done. Make sure the Project Summary now shows the EBAZ as the board part here with a tiny useless image of the board.

Now select "Create Block Design" under "integrator" on the left. It wants a name for the design and suggests "design_1, and why not? Now you get a blank diagram. The big "+" at top center says "add IP". Use this to add "ZYNQ7 Processing System". A colored bar at the top offers/suggests to run "block automation" which never hurts -- do this whenever suggested as it typically indicates that there are things than need to be connected but aren't.

Next I add "AXI gpio" and run block automation again. This connects the gpio to "leds_2bits" which I know are my two red/green LED from the board files. It is interesting (to me) that it just picked these out. I delete them from the diagram and run board automation. Indeed "leds_2bits" is given as an option (and selected by default) in the connection automation dialog. I can select "custom" instead. Now the gpio is connected to something labeled "gpio_rtl".

Don't forget the constraints file

Here is where I now keep the ones that I have used thus far: 
/u1/Projects/Zynq/Ebaz/Ebaz_Master.xdc
/u1/Projects/Zynq/Ebaz/Constraints/ZYBO_Master.xdc
/u1/Projects/FPGA/Zedboard/Zedboard-Master.xdc
Yes, I should create a directory "Zynq/Constraints" and collect them all there side by side, and perhaps someday I will.

I you are like me, you are probably asking, "why don't they just put the doggone constraint file in the same directory as the board files?". The reason why is simple -- the constraint file is project dependent. It may be different for each project, and some projects may not even need a constraint file.

What a constraint file does is to "make the connection" between logical names (like "red_led") that are used in a port in a block diagram, and actual pins on the device. If the PL portion of a project does not require any connections to the outside world, no constraint file is required. Here are two lines from the EBAZ constraint file: 

set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { red_led }];
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { green_led }];
The weird syntax is because this is the tcl language. The logical name "red_led" gets connected to package pin W14. The rest could just be viewed as boilerplate required to fit this into the tcl language used under the hood in Vivado.

To provide a constraint file, here is what you do --- Up and left from your block diagram is a window which typically has the "design" tab selected by default. Select "sources" instead and use the big "+". Select "add or create constraints", then go find the file. One way (other than the above paths) is to select a previous project and copy the file from there. Once you have it selected, ensure that the checkbox to "copy constraint files into project" is selected, then "finish".

The constraints file is what defines "red_led" and "green_led" for the Ebaz, and is what I have always used in my Ebaz designs. I right click in the background of the design and select "create port" in the menu that appears. I make the port an output and change the direction from input to output.

Working with the Vivado block design GUI

The GUI is pretty barbaric. You can drag a line to connect blocks. Wait until you see the line become dark to indicate that the connection has been made. You click on blocks to select them, then do things with them. Dragging around to select and delete does not work, it just zooms to the selected area. There is a zoom out icon in the menu at the top.

Getting the GPIO connected to multiple ports seems to involve hand editing of a "wrapper file", and may not involve ports in the block diagram at all. Something for the future.

What I did in the past was to get the AXI gpio block to have a 32 bit output, i.e. 31:0 and then route that to a 32 bit input on an RTL block I made. The RTL block had separate one bit outputs that I routed to ports named "red_led" and "green_led".

What about Vivado and EMIO?

Clock on the Zynq block to get a menu, then select "customize block". Or just doublt click on the Zynq block. A big GUI thing with lots of green appears.

The right side is page Navigator, and mid way down is MIO configuration.
Inside of this look for I/O Peripherals, expand this and look for GPIO, expand this.
Check the EMIO checkbox, select 4 as the width, click OK.
Now on the Zynq block, there appears a thing "GPIO_0" that is newly created.

It seems that you have to deal with however many pins of EMIO you need as a bundle at this level. You can route these to some RTL block and use verilog to split things up -- at least that is what I do.
Feedback? Questions? Drop me a line!

Tom's Computer Info / [email protected]